The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a mask programmable read-only memory (PROM) cell that is formed utilizing a vertical transistor processing flow.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source and drain located at opposing ends of the semiconductor pillar. One advantage of a vertical transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. As such, vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
Floating gate memory cells, which form the basis of non-volatile memory such as, for example, flash, PROM, EPROM and EEPROM memory are crucial to the implementation of any technology. A PROM (i.e., programmable read-only memory) is a form of a digital memory where the setting of each bit is typically locked by a fuse element or an antifuse element. The data within a PROM is permanent and cannot be changed. The data within conventional PROMs is programmed after manufacturing the memory cell. In typically PROM cells, the transistors are formed utilizing non-vertical transistor technology. In view of the advantages with vertical transistor designs, there is a need for providing a PROM cell using vertical transistor technology in which programming of the PROM may be formed during, rather than after, the manufacturing process.